TAIPEI (Taiwan News) — Qualcomm unveiled a new chip architecture it says could challenge Nvidia’s dominance by eliminating the need for high-bandwidth memory, Nikkei Asia reported Wednesday.
The San Diego-based company introduced the concept during its recent investor day in New York. Executives outlined a multi-year roadmap for a new data center brand called Dragonfly, built around what it calls high-bandwidth compute (HBC).
At the center of the design is a stacked memory approach that places low-power DRAM chips directly on top of the logic die, replacing the traditional use of high-bandwidth memory (HBM) positioned beside the processor. Qualcomm says this reduces data travel distance, cuts energy consumption, and increases efficiency.
In current AI accelerators such as Nvidia’s GPUs, HBM is connected through a silicon interposer, requiring frequent back-and-forth data movement between memory and compute. That process has become a growing bottleneck as AI workloads expand, particularly in inference applications.
Qualcomm claims its HBC architecture can deliver up to six times higher bandwidth per watt compared with HBM-based designs. The company also argues that closer integration of memory and compute will improve performance while lowering energy costs in large-scale data centers.
CEO Cristiano Amon said during investor day that cloud and AI customers are open to new entrants in the market, arguing that competition will accelerate innovation rather than displace existing leaders. Nvidia currently holds more than 90% of the AI accelerator market.
The company plans a broader push into data centers beyond AI accelerators, outlining four product lines: AI chips based on HBC, data center CPUs, custom ASICs, and connectivity chips. It is targeting NT$159.1 billion (US$5 billion) in data center revenue by fiscal 2027 and NT$477.5 billion by 2029. This would mean more demand for TSMC’s capacity.
If achieved, that growth would significantly expand Qualcomm’s non-handset business, which the company expects to reach NT$1.3 trillion by 2029, nearly doubling prior forecasts.
However, analysts remain cautious about whether the new architecture can match or outperform established HBM-based systems at scale. Morningstar analyst Jing Jie Yu said the concept makes sense in theory, but real-world efficiency will depend on detailed specifications and commercial implementation.
Yu also noted that similar “near-memory compute” approaches have been explored by SK Hynix and Samsung Electronics through technologies such as accelerator-in-memory and processing-in-memory, though neither has reached mass production.
Qualcomm executives said their advantage lies in packaging expertise developed through decades of smartphone chip design, including through-silicon via technology. They said this know-how allows them to integrate stacked memory more reliably into commercial products.
The first AI accelerator using HBC is scheduled to ship with Qualcomm’s AI250 data center rack in fiscal 2027, marking the company’s first major entry into the AI infrastructure market dominated by Nvidia.
