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Taiwan’s TSMC unveils 2nm process node

2nm chips will be TSMC’s first to use gate-all-around field-effect transistors

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TSMC. (Reuters photo)

TSMC. (Reuters photo)

TAIPEI (Taiwan News) — Taiwan Semiconductor Manufacturing Co. (TSMC) unveiled its 2-nanometer (N2) process node on Thursday (June 16) at its 2022 TSMC Technology Symposium.

TSMC’s 2nm chips will be the first node that uses gate-all-around field-effect transistors (GAAFETs), according to Tom’s Hardware. The N2 process node has two important innovations that increase performance-per-watt capabilities: nanosheet transistors and backside power rail, the report notes.

Gate-all-around nanosheet transistors have channels surrounded by gates on all four sides to reduce leakage, while their channels can be widened to boost drive current and increase performance or cut back on power consumption and cost, per Tom’s Hardware. To deal with resistance in the back-end-of-line, TSMC has chosen to use backside power delivery to provide the nanosheet transistors with sufficient power, Tom’s Hardware said.

The Taiwanese chipmaker said its 2nm process node has 10-15% higher performance at the same power and complexity, in addition to 25-30% lower power consumption at the same frequency and transistor count when compared to its 3nm N3E chips. Meanwhile, the new node only increases chip density by around 1.1 times compared to N3E, Tom’s Hardware said.

TSMC expects to start volume production of its 2nm chips in the second half of 2025. This means that products using N2 chips will most likely hit the market in late 2025 or 2026.