TAIPEI (Taiwan News) — Taiwan Semiconductor Manufacturing Co. (TSMC) said the development of its upcoming 3 nm process is ahead of schedule.
Chairman Mark Liu (劉德音) gave an update during an online talk at the International Solid-State Circuits Conference (ISSCC) earlier this week, according to CNA. However, Liu did not specify how far ahead the 3 nm progress was.
Liu added that TSMC’s 3 nm process will continue to use the fin field-effect transistor (FinFET) architecture. According to the company, the logic density of its 3 nm chips will be 75 percent higher, 15 percent more efficient, and require 30 percent less power than its currently most advanced commercially produced 5 nm chips.
The world’s largest contract chipmaker had previously said its 3 nm chips would be ready for trial production later this year at a new wafer facility located in the Southern Taiwan Science Park in Tainan, and they would be ready for volume production in the latter half of 2022.
Liu also said that after its 3 nm process, TSMC would adopt the more sophisticated GAA (gate-all-around) transistor structure for its 2 nm process. The company is planning on building the 2 nm fab in Hsinchu, but has yet to release a timetable for the development.